1. Field of the Invention
The present invention relates to a circuit board test system which includes a test apparatus and a circuit board for carrying out tests such as a confidence test of the circuit board, and to a circuit board which is capable of constituting such a circuit board test system.
2. Description of the Related Art
It is often required to determine whether the traces on a circuit board have been patterned as designed or the circuit blocks (circuit elements) implemented on the board will function as specified. This can be achieved through a determination of whether a predetermined output results from a predetermined port when a necessary stimulus is provided to the circuit board to cause the output to be generated from the port.
To carry out such tests, the following circuit board test systems have been conventionally employed. That is, available is one system in which a CPU for applying a test program is additionally mounted on a subject circuit board as well as the other system in which a CPU mounted to perform its inherent functions on a subject circuit board is allowed to apply a test program. Such a test program is stored beforehand in a ROM implemented on the subject circuit board and allows the CPU to successively write data (8-bit data, 16-bit data etc.) into logical addresses each assigned to a circuit block on the circuit board. Then, it is checked if the circuit board works properly in accordance with a determination of whether all data thus written have actually accepted by the circuit blocks mapped to the logical addresses. For example, if the circuit block is a memory, the test program causes the CPU to write the predetermined data to the logical address assigned to the memory. Then, the test program causes the CPU to read it and to compare the read data with the written data. If the two data match, it is determined that the circuit board (memory) works properly. As another example, if the circuit block is an output port, the test program then causes the CPU to write the predetermined data to the logical address assigned to the output port. Thus, if the written data is outputted from the output port, it is determined that the circuit board (output port) works properly.
Conventionally, such a test program contains a multiple of processing modules each of which is for checking its own circuit block and is activated by an individual command. FIG. 11 is a flowchart outlining the logical flow of such a conventional test program. As shown in FIG. 11, in step S501 or the first step after having been activated, the test program waits for a command from a test apparatus connected to a subject test board and receives the command. After having received the command, the test program analyzes the command in step S502 and recognizes processing to be performed. Then, the test program performs the processing (processing 1 to processing Z) corresponding to the command in a step among step S503_1 to S503_Z. In any case, the test program sends a response including the processing result to the test apparatus in the next step S504 and then allows control to return to step S501.
FIG. 12(a) shows the format of a test command for instructing a conventional test program to perform any processing and FIG. 12(a) shows the format of response data. As shown in FIG. 12(a), the test command consists of one byte of Command Code (CC). On the other hand, as shown in FIG. 12(b), the format of the response data corresponding to the test command consists of Response Data (RD) representative of success, failure or the like.
For example, suppose CC=A is associated with the writing of data=0x01 to logical address=0x1000000. Under this condition, as shown in the sequence diagram of FIG. 13, when an operator (tester) of the test apparatus instructs a test apparatus to send a test command of CC=A to a subject test board in order to execute a test on the logical address=0x10000000, the CPU that is provided on the subject test board and has read a test program executes the writing of data=0x01 to logical address=0x10000000 (step S503 in FIG. 11). After the writing has been completed, the CPU sends the response data of RD representative of the current state to the test apparatus. When the tester has been able to confirm that the test apparatus has received RD=S representative of success and that the data=0x01 has accepted by the circuit block mapped to logical address=0x10000000, the tester recognizes that the circuit board works properly with respect to the circuit block.
In addition, suppose CC=B is associated with the reading of the checksum of a ROM implemented on the subject test board. Under this condition, when the tester instructs the test apparatus to send a test command of CC=B to the subject test board, the CPU that has read the test program reads the checksum from the logical address where the checksum of the ROM is stored (step S503 in FIG. 11). After the reading has been completed properly, the CPU sends to the test apparatus the response data of RD representative of the checksum that has been read.
The aforementioned conventional circuit board test system, however, has presented the following problems. That is, since different circuit blocks are mapped to the address space in accordance with the type of individual circuit boards, the subject test boards of different configurations require test programs with the program codes combined differently. In addition, since such a test program organized differently for each subject test board is typically stored on the mask ROM implemented on the subject test board, it was impossible to make a change in or add a test item to the test program after the subject test board has been assembled. Furthermore, a subject test board to be tested on a wide range of test items would require a multiple of processing modules, thereby causing the volume of the entire test program to be significantly increased.
It is an object of the present invention to provide a circuit board test system with a general-purpose test program which is loaded on a subject test board and independent of the hardware configuration of the board, thereby allowing the size of the test program to be reduced and facilitating the change of the test items. It is another object of the present invention to provide a circuit board that can constitute such a circuit board test system.
A circuit board test system according to the present invention developed to achieve the aforementioned objects includes a subject test board having a controller and circuits mapped in an address space of the controller and implemented thereon, and a test apparatus for issuing a test command to the subject test board. The test apparatus includes a command generator part for generating a test command which specifies an address in address space and an operation to be performed to the address, and a command transmitter part for sending the test command generated by the command generator part to subject test board. The subject test board includes a command receiver part for receiving test command, a control part, and a storage part for storing a program to allow the control part to receive a test command via command receiver part and to perform the operation specified by the test command to the address specified by the test command.
With such a configuration, it is possible for the control part of the subject test board to operate data at various addresses in accordance with the contents of the test command sent from the test apparatus to the subject test board without changing the program codes stored in the storage part of the subject test board. Thus, even when the subject test board is to be tested on a wide range of test items, the volume of the program codes is made constant. In addition, it is not necessary to make the program codes to be adapted to the specification of the subject test board. This makes it unnecessary to modify the program codes even for an increase in type of the subject test board, an increase in test item, or a change in hardware configuration of the subject test board.
The circuit board test system according to the present invention may be realized by using the test apparatus including a command generator part which generates a test command that specifies an address in that address space and also specifies the operation is a write operation of particular data to the address. However, it is desirable to use the test apparatus including a command generator part which generates a test command that specifies an address in that address space and data with which a write operation to be performed to the address.
If this configuration is adopted, it is possible to use the program that allows, when received is the test command specifying the data to be written, the control part to write data specified by the test command to and then read the data from the address specified by the test command.
Moreover, the circuit board test system according to the present invention may be realized by using the test apparatus including a command generator part which generates a test command which specifies an address in address space and also specifies that the operation to be performed is a read operation.
Furthermore, in realizing the circuit board test system according to the present invention, it is desirable to create the program so that the control part sends the data having been read to the test apparatus.
A circuit board according to the present invention has a controller and circuits mapped in an address space of the controller and implemented thereon. The circuit board includes a command receiver part for receiving a test command specifying an address in the address space and an operation to be performed to the address. The circuit board also includes a control part, and a storage part for storing a program to allow the control part to receive a test command via the command receiver part and to perform the operation specified by the test command to the address specified by the test command.
Using this circuit board, it is possible to construct the circuit board test system according to the present invention.